1. Technical Field
The present disclosure relates to a method for fabricating a semiconductor device, and, more specifically, to a method for fabricating a semiconductor device using a modeling algorithm to model the proximity effect from the sub-layer on the critical dimensions on a wafer.
2. Discussion of the Related Art
Various circuit elements, such as transistors having a gate disposed between source and drain regions, are integrated in semiconductor devices manufactured by photolithography. Photolithography is a process used in microfabrication of integrated semiconductor devices by using light to transfer a geometric pattern from a photo mask to a light-sensitive chemical photoresist on the substrate. As a circuit pattern to be formed on a wafer is increasingly smaller in size, it becomes more difficult to form a design pattern to the desired shape and dimensions on the wafer. As a result of the miniaturization of the mask pattern, any deviations of the path of light due to a variety of processing conditions, known as optical proximity effects (OPE) or process proximity effects (PPE), become enhanced, and require correction.
In order to limit an influence of the OPE or PPE, optical proximity correction (OPC) or process proximity correction (PPC) is performed, which are techniques of forming the designed resist patterns by using corrected photo masks that are adjusted based on an error calculation. The error calculation may be arrived at through modeling the optical and process proximity effects using algorithms which incorporate various simulation parameters related to, for example, the light sources and the resists being used. Use of OPC/PPC makes it possible to suppress unwanted fluctuations of a critical dimension (CD) on the wafer, such as, for example, line widths that are narrower or wider than designed, so that the original designed layout or as close to the original designed layout as is possible can be reproduced in the wafer.
Conventional modeling algorithms use simulation parameters that address the field and gate polysilicon layers themselves. However, none of known the modeling algorithms use parameters based on the characteristics of an active layer (referred to as a sub-layer) positioned below a gate polysilicon layer.
Accordingly, a need exists for modeling algorithms for modeling proximity effects which take into account the impact from sub-layers, such as an active layer positioned below a gate polysilicon layer.